25 August 2026

69 new posts across 3 semiconductor sources — 6 worth your time.

One week of Chips & Silicon, 6 stories, as published.

CFETs Forge Better Connections

Intel, Samsung, TSMC, and IBM are adopting different nanosheet tier connection methods for Complementary FETs (CFETs), but all are standardizing on direct backside vias for power delivery. The process involves ALD dielectrics, workfunction-optimized metals, and virtual simulation to accelerate yield pathfinding.

Why it matters — Direct backside vias are the industry-wide standard for implementing backside power delivery in CFET architectures.

Semiconductor Engineering · 25 August 2026 · Read the original →

Memory & Storage

How Will The Custom HBM Business Work?

HBM4 introduces a customizable base die, allowing hyperscalers to tailor memory for specific workloads. This shift moves memory makers away from designing all layers and creates a new demand for specialized design teams and EDA tools.

Why it matters — HBM4 transitions the base die from a standard memory component to a customizable logic layer for hyperscalers.

Semiconductor Engineering · 25 August 2026 · Read the original →

AI Accelerators

HP1800: The Magic of Single-Stage 48V to Ultra-Low Voltage

Modern data centers are adopting single-stage 48V to ultra-low voltage conversion to meet the power demands of AI factory infrastructure. This approach follows Nvidia's blueprint for power delivery and aligns with OCP Global Summit standards.

Why it matters — Single-stage conversion from 48V to ultra-low voltage is the efficiency benchmark for next-generation AI power delivery.

EE Times · 25 August 2026 · Read the original →

AI Accelerators

Nvidia’s Inference Pivot Reaches Rebellions in Korea

Nvidia is reportedly expanding its inference silicon strategy through an unconventional deal with Groq for a nonexclusive technology license. The move also involves engagement with Rebellions in Korea as Nvidia seeks to maintain dominance beyond AI training.

Why it matters — Nvidia is using nonexclusive technology licensing to accelerate its entry into the specialized AI inference market.

EE Times · 25 August 2026 · Read the original →

Packaging

Hot Chips 2026: SK hynix pushes hybrid bonding to HBM5 as AI memory hits 775-micron ceiling — firm extends MR-MUF through Nvidia Rubin

SK hynix is transitioning to hybrid bonding for its upcoming HBM5 memory to overcome the 775-micron package height limit. The company plans to extend its existing Mass Reflow Molded Underfill (MR-MUF) packaging technology through the Nvidia Rubin architecture generation.

Why it matters — The physical 775-micron height limit for HBM is forcing an industry-wide transition from microbump-based MR-MUF to hybrid bonding.

Tom's Hardware · 25 August 2026 · Read the original →

Packaging

Hot Chips 2026: Intel Xeon 7 'Diamond Rapids' comes with up to 256 P-cores, 1.28 GB of last-level cache — next-gen 18A-P CPU also brings AVX 10.2 and uses UCIe-S instead of EMIB

Intel's next-generation Xeon 7 'Diamond Rapids' processors, built on the 18A-P process node, will feature up to 256 P-cores and 1.28 GB of last-level cache. The architecture adopts the open UCIe-S standard for die-to-die interconnects, replacing Intel's proprietary EMIB packaging.

Why it matters — Transitioning from proprietary EMIB to UCIe-S signals a major industry shift toward standardized, open-specification die-to-die interconnects in multi-die processors.

Tom's Hardware · 25 August 2026 · Read the original →

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