01 September 2026

70 new posts across 3 semiconductor sources — 7 worth your time.

One week of Chips & Silicon, 7 stories, as published.

Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations

The semiconductor industry is preparing to transition to CFET-based transistor architectures starting at the A7 logic technology node. This shift, supported by research from imec, enables standard cells of 4.5-track (4.5T) and below by utilizing novel integration modules and complementary p- and n-type transistor configurations.

Why it matters — Standard cell heights can be reduced to 4.5-track and below by transitioning to CFET architectures at the A7 node and beyond.

Semiconductor Engineering · 01 September 2026 · Read the original →

Process & Fabs

M3D 6T SRAM With BEOL Pass-Gates at 2nm (Georgia Tech, Synopsys)

Researchers from Georgia Tech and Synopsys proposed a process-aware monolithic-3D (M3D) 6T SRAM design targeted at the 2nm node. The architecture integrates back-end-of-line (BEOL) indium gallium zinc oxide (IGO) pass-gates with an all-silicon nanosheet latch, buried power rails, and ruthenium (Ru) interconnects.

Why it matters — Monolithic-3D 6T SRAM at the 2nm node can be realized by integrating BEOL IGO pass-gates with an all-silicon nanosheet latch and ruthenium interconnects.

Semiconductor Engineering · 01 September 2026 · Read the original →

AI Accelerators

First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC

OpenAI's VP of hardware, Richard Ho, presented the first benchmark results for 'Jalapeño,' a clean-sheet general-purpose AI accelerator ASIC. The chip was designed from the ground up specifically to optimize the execution of large language models (LLMs).

Why it matters — OpenAI has developed a clean-sheet custom ASIC, Jalapeño, specifically optimized for LLM workloads, signaling a shift toward first-party hardware design.

EE Times · 01 September 2026 · Read the original →

Packaging

SK Hynix’s $4B HBM Project Targets U.S. Chipmaking Gap

SK Hynix is investing $4 billion to construct its first advanced packaging facility in the United States, specifically targeting high-bandwidth memory (HBM). The project is designed to address a critical manufacturing and packaging vulnerability within the domestic U.S. semiconductor supply chain.

Why it matters — A $4 billion investment in domestic U.S. HBM advanced packaging aims to close a key geographic vulnerability in the AI hardware supply chain.

EE Times · 01 September 2026 · Read the original →

Memory & Storage

China's CXMT beats Western chipmakers to announcement of LPDDR6 mass production — Xiaomi smartphones to debut industry’s first LPDDR6 chips

Chinese memory manufacturer CXMT has announced the mass production of LPDDR6 memory chips, ahead of its Western competitors. The new low-power memory chips are scheduled to make their market debut in upcoming Xiaomi smartphones.

Why it matters — CXMT has achieved mass production of LPDDR6 ahead of Western competitors, establishing an early market footprint in next-generation mobile memory.

Tom's Hardware · 01 September 2026 · Read the original →

Policy & Export

Key Nvidia and Intel supplier raided over alleged China origin fraud — Unimicron faces probe over PCB origin washing, risk of 40% U.S. tariff penalty

Key Nvidia and Intel supplier Unimicron was raided over alleged China origin fraud. The company faces a probe over PCB origin washing, risking a 40% U.S. tariff penalty.

Why it matters — A major packaging and PCB supplier facing a 40% tariff penalty highlights how geopolitical origin-tracing and compliance audits can instantly disrupt the semiconductor packaging supply chain.

Tom's Hardware · 01 September 2026 · Read the original →

Process & Fabs

Intel Details 18A-P, 14A Progress, New Xeon & Core CPUs

Intel announced significant progress on its 18A and 14A process nodes, with 18A yields beating internal milestones and 14A defect density improving faster than expected. The company detailed its upcoming Diamond Rapids Xeon 6+ processors, featuring up to 256 e-cores on 18A-P with Foveros Direct 3D and UCIe-S, and revealed that its budget-focused Wildcat Lake Core Ultra Series 3 also leverages 18A for compute and UCIe.

Why it matters — Chip designers using Intel Foundry's 18A-P can leverage a 30% frequency gain at 0.5V, while UCIe-S adoption in new CPUs simplifies multi-die integration across product tiers.

intel.com · 01 September 2026 · Read the original →

Designing for nodes we cannot build, using supply chains we cannot trace.

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