08 September 2026

69 new posts across 3 semiconductor sources — 9 worth your time.

One week of Chips & Silicon, 9 stories, as published.

When the Package Becomes an Electrical Design Variable

Explores how advanced AI systems shift voltage stability challenges from the board-level power delivery network (PDN) to the package level. It explains why the package has become a critical electrical design variable for managing short, high-speed power paths.

Why it matters — Shifting power delivery network (PDN) design from the board level to the package level is required to maintain voltage stability over ultra-short, high-current paths in AI servers.

EE Times · 08 September 2026 · Read the original →

AI Accelerators

What Can Go Wrong In 800VDC AI Data Centers

Details the safety and reliability challenges of transitioning AI data centers to 800VDC power delivery, including electrical faults, arc flashes, and thermal runaways. It highlights the need to adopt automotive-grade chip reliability technologies and solid-state protection components.

Why it matters — High-voltage (800VDC) AI data centers must adopt automotive-grade chip reliability standards, hot-swap circuits, and solid-state circuit breakers to mitigate severe electrical faults and thermal runaways.

Semiconductor Engineering · 08 September 2026 · Read the original →

AI Accelerators

Humanoid Compute, Security More Complex Than AVs

Discusses the hybrid, distributed compute architectures required for humanoid robots. It details the combination of AI-enabled MCUs/NPUs for localized processing in limbs with centralized GPUs and FPGA-based sensor bridges for global inputs.

Why it matters — Humanoid robotics requires a hybrid architecture of localized edge MCUs/NPUs for low-latency limb control paired with a centralized GPU and FPGA sensor bridge for global processing.

Semiconductor Engineering · 08 September 2026 · Read the original →

Memory & Storage

Kioxia’s Flash-for-DRAM Initiative Eyes AI Workloads

Covers Kioxia's development of a Compute Express Link (CXL) flash memory module designed to replace expensive DRAM with high-density flash for specific AI memory workloads.

Why it matters — Utilizing CXL-connected flash modules to replace DRAM for specific AI workloads offers a lower-cost scaling path for memory-intensive models.

EE Times · 08 September 2026 · Read the original →

Process & Fabs

Intel surpasses one million High-NA EUV wafers processed, outpaces the rest of the industry combined — company also trailblazing giant 6×12 photomasks to speed production and lower costs

Intel has processed over one million wafers using High-NA EUV lithography, leading the industry's adoption of the technology. To optimize production throughput and lower manufacturing costs, the company is also introducing massive 6x12 photomasks.

Why it matters — Transitioning to larger 6x12 photomasks addresses the field-size limitations of High-NA EUV, allowing chipmakers to maintain throughput without doubling mask costs.

Tom's Hardware · 08 September 2026 · Read the original →

Design & EDA

Arm debuts next-gen semi-custom Neoverse CSS N4 ‘Ranger’ platform — compute subsystem packs up to 128 cores per die on TSMC N3P

Arm has introduced its next-generation Neoverse CSS N4 'Ranger' platform, a semi-custom compute subsystem. The architecture is designed to pack up to 128 cores per die and is targeted for fabrication on TSMC's N3P process node.

Why it matters — Utilizing pre-designed compute subsystems on TSMC N3P allows custom silicon designers to scale to 128 cores while minimizing physical implementation risks on advanced nodes.

Tom's Hardware · 08 September 2026 · Read the original →

Process & Fabs

Samsung, ASML Expand High NA EUV Collaboration

Samsung Electronics and ASML expanded their strategic partnership, with Samsung joining an industry initiative to advance next-generation 12-inch photomask technology for High NA EUV. Samsung plans to adopt High NA EUV for future DRAM manufacturing.

Why it matters — Samsung's commitment to 12-inch photomasks and High NA EUV for DRAM manufacturing signals a critical shift in memory production, enabling denser and more efficient future memory chips.

news.samsung.com · 08 September 2026 · Read the original →

Packaging

TSMC VP: Silicon Photonics to Dominate AI

TSMC Vice President K.C. Hsu stated that silicon photonics will play a dominant role in AI growth by 2027, enabling chip-level co-packaged optics (CPO). TSMC is on track to begin CPO production later in 2026, with optical transceiver sales accelerating at 50% annually.

Why it matters — TSMC's impending CPO production confirms a major shift in packaging for AI, addressing critical bandwidth and power efficiency challenges in data centers.

taipeitimes.com · 08 September 2026 · Read the original →

Packaging

Innolux, AUO Enter AI Chip Packaging

Taiwan display manufacturers Innolux and AUO are expanding into the semiconductor supply chain, leveraging their display technology for AI chip packaging solutions including FOPLP, glass substrates, and Micro LED Co-Packaged Optics (CPO).

Why it matters — New entrants from the display industry bring alternative manufacturing techniques and materials to advanced packaging for AI, potentially increasing innovation and capacity.

digitimes.com · 08 September 2026 · Read the original →

Remember when we only had to design the silicon?

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